Superconducting integrated circuits (ICs) based on Josephson junctions (JJs) are capable of operation with very low power and high speed, orders of magnitude beyond those possible using conventional semiconducting circuits. Recently, superconducting single flux quantum (SFQ) circuits have progressed to even lower power versions with zero-static power dissipation (Mukhanov, U.S. Pat. No. 8,571,614; Herr, U.S. Pat. No. 7,852,106), making them highly competitive for application in next generation energy-efficient computing systems. However, the practical realization of superconducting digital circuits for high-end computing requires a significant increase in circuit complexity and gate density. Conventional SFQ integrated circuit fabrication technology has been proven to deliver SFQ digital ICs with more than 10,000 JJs per die, using a fabrication process with just 4 superconducting niobium (Nb) layers and relatively coarse (1.0 μm) lithography with 1.5-2 μm minimum JJ size, without layer planarization. Further increase in integration density and scale of superconducting ICs requires finer lithography to reduce the size of all circuit components including JJs, vias, thin-film inductors, thin-film resistors, and interconnects. Note that this is a different application than superconducting quantum computing based on similar JJs, for which the required circuit complexity is significantly less, but the operating temperature is much lower (see, e.g., Ladizinsky, US20110089405).
The biggest gain in the IC integration scale can be achieved by adding more superconducting layers using layer planarization, which becomes essential to avoid problems associated with lines over edges. Hinode (U.S. Pat. No. 7,081,417) has demonstrated up to 10 Nb layers with submicron JJ size using planarization based on chemical mechanical polishing (CMP). CMP is generally the rate-limiting step in the overall process, and can also lead to contamination, given that it is a wet process that may generate particulate residues. Another known problem with CMP is that the layer planarization rate may depend on the detailed pattern and scale of the devices in a given layer, and may therefore vary within a layer and between layers. One solution to this problem is to incorporate standard dummy patterns in sparsely populated regions (see, e.g., Chen, U.S. Pat. No. 7,235,424). In contrast, Hinode developed a process without such dummy patterns, but using an inverted mask and etching to create a narrow standard “Caldera” (or crater edge) at all edges. Overall, this creates structures that are largely independent of pattern and scale, permitting control and uniformity of the CMP process.
In order to obtain the greatest increase in circuit density by adding superconducting layers, one needs stackable vias (or plugs) allowing connection between multiple metal layers with minimal parasitic inductance, while not compromising circuit area. This has been a difficult problem requiring the development of special fabrication techniques (e.g., Tolpygo, U.S. Pat. Nos. 8,301,214; 8,437,818).
In general, any fully planarized process requires one step of planarization (using, e.g., CMP) for each patternable layer. For example, consider a basic wiring bi-layer such as that shown in FIG. 25A, comprising a lower wiring layer and an upper insulating layer. The insulating layer must contain holes which are penetrated by conducting vias that can connect the lower wiring layer to other wiring layers above. A standard planarized process would comprise first patterning the metals and insulators in the bottom wiring layer, followed by a first planarization step leading to the intermediate structure in FIG. 25B. This would be followed by depositing and patterning the insulator and metal in the top insulator/via layer, followed by a second planarization step.
The art fails to provide a multi-layer planarization process that requires only a single step of chemical mechanical polishing for each wiring bi-layer.
Planarized superconducting circuit technology is discussed in:
Tolpygo, Sergey K., et al. “System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuits.” U.S. Pat. No. 8,437,818, 7 May 2013.
Tolpygo, Sergey K., et al. “Deep Sub-Micron Stud-Via Technology for Superconductor VLSI Circuits,” arXiv preprint arXiv:1309.7505 (2013).
Kirichenko, Alex F., et al. “Demonstration of an 8×8-bit RSFQ multi-port register file.” Superconductive Electronics Conference (ISEC), 2013 IEEE 14th International. IEEE, 2013.
Berggren, Karl K., et al. “Low Tc superconductive circuits fabricated on 150-mm-diameter wafers using a doubly planarized Nb/AlOx/Nb process.” Applied Superconductivity, IEEE Transactions on 9.2 (1999): 3271-3274.
Satoh, Tetsuro, et al. “Fabrication process of planarized multi-layer Nb integrated circuits.” Applied Superconductivity, IEEE Transactions on 15.2 (2005): 78-81.
Ketchen, M. B., et al. “Sub-μm, planarized, Nb—AlOx—Nb Josephson process for 125 mm wafers developed in partnership with Si technology.” Applied physics letters 59.20 (1991): 2609-2611.
Nagasawa, S., et al. “Development of advanced Nb process for SFQ circuits.” Physica C: Superconductivity 412 (2004): 1429-1436.
Nagasawa, S., et al. “New Nb multi-layer fabrication process for large-scale SFQ circuits.” Physica C: Superconductivity 469.15 (2009): 1578-1584.
Nagasawa, Shuichi, et al. “Planarized multi-layer fabrication technology for LTS large-scale SFQ circuits.” Superconductor Science and Technology 16.12 (2003): 1483.
Abelson, Lynn A., and George L. Kerber, “Superconductor integrated circuit fabrication technology.” Proceedings of the IEEE 92.10 (2004): 1517-1533.
Patel, Vijay, and J. E. Lukens, “Self-shunted Nb/AlOx/Nb Josephson junctions.” Applied Superconductivity, IEEE Transactions on 9.2 (1999): 3247-3250.
Hidaka, M., et al, “Current status and future prospect of the Nb-based fabrication process for single flux quantum circuits.” Superconductor Science and Technology 19.3 (2006): S138.
Sauvageau, J. E., et al. “Superconducting integrated circuit fabrication with low temperature ECR-based PECVD SiO2 dielectric films.” Applied Superconductivity, IEEE Transactions on 5.2 (1995): 2303-2309.
Castellano, Maria Gabriella, et al. “Characterization of a fabrication process for the integration of superconducting qubits and rapid-single-flux-quantum circuits.” Superconductor Science and Technology 19.8 (2006): 860.
Okanoue, K. U. M. I., and K. Hamasaki. “Temperature dependence of the return current in BiSrCaCuO stacks fabricated by self-planarizing process.” Applied Physics Letters 87 (2005): 252506.
Ketchen, M., et al. “Octagonal washer DC SQUIDs and integrated susceptometers fabricated in a planarized sub-μm Nb—AlOx—Nb technology.” Applied Superconductivity, IEEE Transactions on 3.1 (1993): 1795-1799.
Hidaka, Mutsuo, et al, “Improvements in fabrication process for Nb-based single flux quantum circuits in Japan.” IEICE transactions on electronics 91.3 (2008): 318-324.
Brock, Darren K., et al. “Retargeting RSFQ cells to a submicron fabrication process.” Applied Superconductivity, IEEE Transactions on 11.1 (2001): 369-372.
Tahara, Shuichi, et al. “Superconducting digital electronics.” Applied Superconductivity, IEEE Transactions on 11.1 (2001): 463-468.
Tolpygo, Sergey K., et al. “20 kA/cm2 process development for superconducting integrated circuits with 80 GHz clock frequency.” IEEE Trans. Appl. Supercond 17.2 (2007): 946-951.
Bao, Z., et al. “Fabrication of high quality, deep-submicron Nb/AlOx/Nb Josephson junctions using chemical mechanical polishing.” Applied Superconductivity, IEEE Transactions on 5.2 (1995): 2731-2734.
Bhushan, M., R. Rouse, and J. E. Lukens. “Chemical-Mechanical Polishing in Semidirect Contact Mode.” Journal of the Electrochemical Society 142.11 (1995): 3845-3851.
Lichtenberger, A. W., et al. “Fabrication of micron size Nb/Al—Al2O3/Nb junctions with a trilevel resist liftoff process.” Magnetics, IEEE Transactions on 27.2 (1991): 3168-3171.
LeDuc, H. G., et al. “Submicron area NbN/MgO/NbN tunnel junctions for SIS mixer applications.” Magnetics, IEEE Transactions on 27.2 (1991): 3192-3195.
Satoh, Tetsuro, et al. “Improvement of Fabrication Process for 10-kA/cm2 Multi-Layer Nb Integrated Circuits” Applied Superconductivity, IEEE Transactions on 17.2 (2007): 169-172.
Bhushan, M., and E. M. Macedo. “Nb/AlOx/Nb trilayer process for the fabrication of submicron Josephson junctions and low-noise dc SQUIDs.” Applied physics letters 58.12 (1991): 1323-1325.
Silver, A., et al. “Development of superconductor electronics technology for high-end computing,” Superconductor Science and Technology 16.12 (2003): 1368.
Akaike, H., et al. “Demonstration of a 120 GHz single-flux-quantum shift register circuit based on a 10 kA cm−2 Nb process.” Superconductor Science and Technology 19.5 (2006): S320.
Akaike, H., et al. “Design of single flux quantum cells for a 10-Nb-layer process.” Physica C: Superconductivity 469.15 (2009): 1670-1673.
Numata, Hideaki, and Shuichi Tahara. “Fabrication technology for Nb integrated circuits.” IEICE transactions on electronics 84.1 (2001): 2-8.
Dmitriev, Pavel N., et al. “High quality Nb-based tunnel junctions for high frequency and digital applications.” Applied Superconductivity, IEEE Transactions on 13.2 (2003): 107-110.
Chen, W., et al. “Rapid single flux quantum T-flip flop operating up to 770 GHz.” Applied Superconductivity, IEEE Transactions on 9.2 (1999): 3212-3215.
Numata, Hideaki, et al. “Fabrication technology for high-density Josephson integrated circuits using mechanical polishing planarization.” Applied Superconductivity, IEEE Transactions on 9.2 (1999): 3198-3201.
Bunyk, P. I., et al. “High-speed single-flux-quantum circuit using planarized niobium-trilayer Josephson junction technology.” Applied physics letters 66.5 (1995): 646-648.
Gallagher, William J., et al. “Planarization of Josephson integrated circuit.” U.S. Pat. No. 5,055,158. 8 Oct. 1991.
Dolata, R., et al. “Single-charge devices with ultrasmall Nb/AlO/Nb trilayer Josephson junctions.” Journal of applied physics 97 (2005): 054501.
Abelson, Lynn A., et al. “Superconductive multi-chip module process for high speed digital applications.” Applied Superconductivity, IEEE Transactions on 7.2 (1997): 2627-2630.
Chen, Wei, Vijay Patel, and James E. Lukens. “Fabrication of high-quality Josephson junctions for quantum computation using a self-aligned process.” Microelectronic engineering 73 (2004): 767-772.
Hidaka, M.; Nagasawa, S.; Hinode, K.; Satoh, T. “Device Yield in Nb-Nine-Layer Circuit Fabrication Process”, Applied Superconductivity, IEEE Transactions on, On page(s): 1100906-1100906 Volume: 23, Issue: 3, June 2013.
Satoh, T.; Hinode, K.; Nagasawa, S.; Kitagawa, Y.; Hidaka, M.; Yoshikawa, N.; Akaike, H.; Fujimaki, A.; Takagi, K.; Takagi, N. “Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active Layer”, Applied Superconductivity, IEEE Transactions on, On page(s): 167-170 Volume: 19, Issue: 3, June 2009
Kunert, J.; Brandel, O.; Linzen, S.; Wetzstein, O.; Toepfer, H.; Ortlepp, T.; Meyer, H. “Recent Developments in Superconductor Digital Electronics Technology at FLUXONICS Foundry”, Applied Superconductivity, IEEE Transactions on, On page(s): 1101707-1101707 Volume: 23, Issue: 5, October 2013
Satoh, T.; Hinode, K.; Nagasawa, S.; Kitagawa, Y.; Hidaka, M. “Improvement of Fabrication Process for 10-kA/cm2 Multi-Layer Nb Integrated Circuits”, Applied Superconductivity, IEEE Transactions on, On page(s): 169-172 Volume: 17, Issue: 2, June 2007
Nagasawa, S.; Satoh, T.; Hinode, K.; Kitagawa, Y.; Hidaka, M. “Yield Evaluation of 10-kA/cm2 Nb Multi-Layer Fabrication Process Using Conventional Superconducting RAMs”, Applied Superconductivity, IEEE Transactions on, On page(s): 177-180 Volume: 17, Issue: 2, June 2007
Tanabe, K.; Hidaka, M. “Recent Progress in SFQ Device Technologies in Japan”, Applied Superconductivity, IEEE Transactions on, On page(s): 494-499 Volume: 17, Issue: 2, June 2007
Maezawa, M.; Ochiai, M.; Kimura, H.; Hirayama, Fuminori; Suzuki, M. “Design and Operation of RSFQ Cell Library Fabricated by Using a 10-kA/cm2 Nb Technology”, Applied Superconductivity, IEEE Transactions on, On page(s): 500-504 Volume: 17, Issue: 2, June 2007
Hidaka, M; Nagasawa, S; Satoh, T; Hinode, K; Kitagawa, Y “Current status and future prospect of the Nb-based fabrication process for single flux quantum circuits”, Superconductor Science and Technology, Volume. 19, Issue. 3, pp. S138, 2006, ISSN: 09532048.
Akaike, H; Yamada, T; Fujimaki, A; Nagasawa, S; Hinode, K; Satoh, T; Kitagawa, Y; Hidaka, M “Demonstration of a 120 GHz single-flux-quantum shift register circuit based on a 10 kA cm2 Nb process”, Superconductor Science and Technology, Volume. 19, Issue. 5, pp. S320, 2006, ISSN: 09532048.
Strauch, Frederick; Williams, Carl “Theoretical analysis of perfect quantum state transfer with superconducting qubits”, Physical Review B, Volume. 78, Issue. 9, pp. 094516, 2008, ISSN: 10980121.
Mitamura, Naoki; Naito, Naoto; Akaike, Hiroyuki; Fujimaki, Akira “Suppression of Magnetic Flux Trapping by Moats formed in NbN Ground Planes”, Applied Physics Express, Volume. 4, pp. 013102, 2010, ISSN: 18820778.
Bunyk, Paul I.; Johnson, Mark W.; Hilton, Jeremy P., “SUPERCONDUCTING SHIELDING FOR USE WITH AN INTEGRATED CIRCUIT FOR QUANTUM COMPUTING”, U.S. Pat. No. 8,247,799.
Bunyk, Paul I.; Johnson, Mark W.; Hilton, Jeremy P., “SUPERCONDUCTING SHIELDING FOR USE WITH AN INTEGRATED CIRCUIT FOR QUANTUM COMPUTING”, U.S. Pat. No. 7,687,938.
U.S. Pat. Nos. 4,075,756; 4,418,095; 4,437,227; 4,448,800; 4,456,506; 4,904,619; 5,055,158; 5,059,448; 5,063,267; 5,091,162; 5,118,530; 5,173,620; 5,229,360; 5,246,782; 5,246,885; 5,256,636; 5,262,201; 5,291,035; 5,298,875; 5,322,817; 5,326,988; 5,347,086; 5,365,476; 5,388,068; 5,409,777; 5,436,029; 5,476,719; 5,477,061; 5,523,686; 5,529,524; 5,548,181; 5,565,695; 5,587,623; 5,609,925; 5,619,097; 5,625,290; 5,689,087; 5,710,437; 5,730,922; 5,742,459; 5,750,474; 5,753,014; 5,764,567; 5,776,863; 5,786,690; 5,801,393; 5,801,984; 5,818,373; 5,820,923; 5,853,808; 5,912,503; 5,923,970; 6,016,000; 6,023,072; 6,051,440; 6,072,689; 6,110,278; 6,110,392; 6,124,198; 6,157,329; 6,190,998; 6,285,050; 6,306,729; 6,384,423; 6,420,251; 6,429,095; 6,528,814; 6,593,212; 6,600,638; 6,623,355; 6,624,047; 6,642,608; 6,717,845; 6,743,078; 6,777,036; 6,804,146; 6,807,090; 6,807,094; 6,809,959; 6,825,106; 6,849,469; 6,852,167; 6,870,761; 6,911,665; 6,926,921; 6,946,597; 6,967,154; 6,975,533; 6,992,344; 7,042,004; 7,042,035; 7,050,329; 7,064,976; 7,068,535; 7,081,417; 7,106,159; 7,115,218; 7,129,552; 7,142,078; 7,160,577; 7,161,112; 7,166,816; 7,215,570; 7,259,434; 7,269,059; 7,279,732; 7,311,944; 7,319,069; 7,323,348; 7,338,907; 7,339,819; 7,371,698; 7,393,699; 7,396,741; 7,397,060; 7,410,668; 7,456,421; 7,463,512; 7,473,576; 7,476,587; 7,505,310; 7,507,519; 7,510,664; 7,514,367; 7,527,985; 7,534,647; 7,535,035; 7,541,198; 7,541,263; 7,541,558; 7,554,144; 7,554,161; 7,560,337; 7,569,844; 7,595,218; 7,605,079; 7,638,359; 7,642,539; 7,646,570; 7,670,646; 7,682,868; 7,687,938; 7,696,506; 7,697,316; 7,732,003; 7,732,800; 7,741,636; 7,749,854; 7,755,076; 7,759,747; 7,786,461; 7,816,661; 7,820,997; 7,821,747; 7,868,539; 7,870,087; 7,872,291; 7,875,493; 7,879,645; 7,884,342; 7,902,038; 7,932,129; 7,956,344; 7,972,893; 7,984,012; 8,003,410; 8,026,038; 8,032,474; 8,039,392; 8,055,318; 8,062,923; 8,076,242; 8,080,440; 8,106,376; 8,110,456; 8,111,541; 8,114,763; 8,119,020; 8,124,426; 8,124,906; 8,143,150; 8,158,963; 8,168,291; 8,178,388; 8,188,563; 8,189,980; 8,211,833; 8,237,140; 8,237,148; 8,244,662; 8,247,799; 8,253,320; 8,301,214; 8,324,734; 8,330,357; 8,339,030; 8,362,576; 8,383,929; 8,384,060; 8,404,620; 8,437,818; 8,513,637; and 8,536,566.
U.S. Pub. Pat. Appln. Nos. 20020055323; 20020068419; 20020148560; 20020197415; 20030194953; 20040056335; 20040061229; 20040071019; 20040081751; 20040151893; 20040159869; 20040206267; 20040222500; 20040266209; 20050042430; 20050058840; 20050121068; 20050123674; 20050149002; 20050149169; 20050182482; 20050191763; 20050197254; 20050237140; 20050240100; 20050244337; 20050261763; 20050267000; 20050278020; 20060030074; 20060073706; 20060097288; 20060138394; 20060142853; 20060162497; 20060165898; 20060165910; 20060166057; 20060255987; 20060264069; 20060270082; 20060284158; 20060286743; 20070108429; 20070131922; 20070138458; 20070155172; 20070158690; 20070161186; 20070173019; 20070176261; 20070194225; 20070241371; 20070259528; 20070278529; 20070281420; 20070285843; 20070298535; 20080023442; 20080060947; 20080096341; 20080106923; 20080116449; 20080135824; 20080138929; 20080138930; 20080138931; 20080150422; 20080173931; 20080192534; 20080203375; 20080217648; 20080218519; 20080246014; 20080247224; 20080258126; 20080259672; 20080266940; 20080277766; 20090008632; 20090014706; 20090032796; 20090042335; 20090079494; 20090098716; 20090101883; 20090102369; 20090104771; 20090189138; 20090230376; 20090230378; 20090236743; 20090239358; 20090295510; 20100012167; 20100012353; 20100068878; 20100133514; 20100178825; 20100207095; 20100216279; 20100221888; 20100237316; 20100279000; 20100297824; 20110012084; 20110024409; 20110057169; 20110060711; 20110076825; 20110079817; 20110089405; 20110124483; 20110136282; 20110163455; 20110168089; 20110174519; 20110186775; 20110207289; 20110238607; 20120000691; 20120012833; 20120012870; 20120012897; 20120133050; 20120164429; 20120263935; 20130043452; 20130076231; 20130082232; 20130083443; 20130096825; 20130196856; and 20130200429.
Each of the foregoing references and patent documents is expressly incorporated herein by reference in its entirety.